Title :
New designs of Redundant-Binary full Adders and its applications
Author :
Abid, Zine ; Wang, Wei
Author_Institution :
ECE Dept., Univ. of Western Ontario, London, ON
Abstract :
New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case studies, two efficient on-line multipliers are implemented using the new full adders, providing improved performance while requiring lower number of transistors.
Keywords :
CMOS integrated circuits; adders; logic design; redundant number systems; transistors; CMOS technology; power dissipation; redundant-binary full adders; transistor; Adders; Algorithm design and analysis; CMOS technology; Delay effects; Design engineering; Digital arithmetic; Digital systems; Educational institutions; Power dissipation; Voltage;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4542180
