De-synchronization of a point-of-sales digital-logic controller

In this paper, we propose a methodology to de- synchronize a synchronous digital-logic system to obtain a system based-on asynchronous logic with equivalent input/output (I/O) functionality. The motivation is to compare the performance of synchronous and asynchronous implementations, especially on power dissipation and process variation robustness. To de- synchronize the controller, several transformations are made to the synchronous controller, such as (1) removing the clock, (2) replacing registers with asynchronous handshaking latches, (3) inserting matching delays, and (4) inserting pipeline buffers in feedback paths. We apply the de-synchronization methodology to a point-of-sales (POS) digital-logic controller modeled with Verilog hardware description language (HDL), and is based-on the Moore finite state machine (FSM). Gate-level simulation verifies that the asynchronous implementation has equivalent functionality as the synchronous controller. Power simulations show that the asynchronous controller consumes only a fraction of the power (5.4%) of the synchronous controller.