A synchronized variable frequency clock scheme in chip multiprocessors

Dynamic voltage/frequency scaling (DVFS) has been widely applied to reduce the power dissipation of multi-cores processor. However, when applying DVFS, signals need to be synchronized between asynchronous clock domains with overhead of several cycles, which will result in performance penalty, and during frequency scaling the circuit cannot work. This paper proposes a novel variable frequency clock scheme in chip multiprocessors. In our scheme, processor cores running at different frequency can communicate with each other without the overhead of synchronizing signals. The results of simulation show that our scheme can achieve EDP improvement by 16.8%, with only 3.6% performance degradation.