Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis

In this paper, we propose a new architecture for a variable length ring oscillator (VLRO) used in applications such as clock synthesis. With previously proposed VLROs, it was found that a change in length leaves the internal nodes in an unknown state which can cause undesirable behavior. The newly proposed design resolves this problem and guarantees a glitch-free length-change within a single clock cycle. These features have been validated in simulations using 180 nm CMOS technology where a seven-stage VLRO was able to switch between 476 MHz, 595 MHz and 1.05 GHz. The proposed architecture was also validated experimentally on Altera´s Cyclone II FPGA.