Title :
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library
Author :
Wang, Li Rong ; Chiu, Yi Wei ; Hu, Chia Lin ; Tu, Ming Hsien ; Jou, Shyh Jye ; Lee, Chung Len
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Abstract :
In this paper, a 32-bit reconfigurable multiplication- accumulation architecture, which can execute flexibly one 32times32, two 16times16 or four 8times8 two´s complement multiply- accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-Vt CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
Keywords :
CMOS integrated circuits; encoding; power consumption; reconfigurable architectures; mixed-Vt CMOS standard cell library; modified booth encoding; multiplication-accumulation; power consumption; reconfigurable MAC architecture; size 130 nm; storage capacity 32 bit; Computer architecture; Concurrent computing; Digital signal processing; Encoding; Energy consumption; Libraries; Parallel processing; Power dissipation; Signal design; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4542195
