A data traffic efficient H.264 deblocking IP

This paper presents a H.264 deblocking IP that minimizes the data traffic by avoiding repeated read and write operations of the same pixels with the help of local buffers and increased data locality through a functionally equivalent reordering of the deblocking process. The microarchitecture of the IP uses a sophisticated datapath and controller to pipeline the memory access and deblocking steps, leading to full utilization of resources and a minimal cycle count per macroblock. The IP has been prototyped on FPGA, achieving an operating frequency of >100MHz, and it is capable of supporting 720p (1280x720) deblocking at frame rates up to 144 Hz (or higher resolution at lower rate). Its equivalent logic gate count, obtained by synthesis to ASIC technology, is 10.46k excluding SRAMs.