Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits

Author

Baba, Toshio ; Uemura, Tetsuya

Author_Institution

Fundamental Res. Labs., NEC Corp., Ibaraki, Japan

fYear

1998

fDate

27-29 May 1998

Firstpage

7

Lastpage

12

Abstract

Multiple negative-differential-resistance (NDR) characteristics (up to six NDRs) are demonstrated by fabricating multiple-junction surface tunnel transistors (MJ-STTs) using an InGaAs material system. The tunneling current density is 500 times larger than that for a GaAs-based MJ-STT as well as higher peak-to-valley ratios (about 5). As an application of MJ-STTs for binary and multiple-valued logic, a programmable NAND/NOR logic circuit and a three-valued inverter circuit are implemented monolithically. Proper circuit operations of these circuits are confirmed using an oscillatory supply voltage

Keywords

integrated logic circuits; multivalued logic circuits; tunnel transistors; InGaAs; InGaAs-based; multiple-junction surface tunnel transistors; multiple-valued logic circuits; programmable NAND/NOR; three-valued inverter; Gallium arsenide; Indium gallium arsenide; Laboratories; Logic circuits; Logic devices; MONOS devices; National electric code; Pulse inverters; Resonant tunneling devices; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on

Conference_Location

Fukuoka

ISSN

0195-623X

Print_ISBN

0-8186-8371-6

Type

conf

DOI

10.1109/ISMVL.1998.679267

Filename

679267