DocumentCode
1848815
Title
Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm
Author
Kim, Jeong-Hyun ; Chung, Kyusik ; Kim, Young-Jun ; Kim, Seok-Hoon ; Kim, Lee-Sup
Author_Institution
Dept. of EECS, KAIST, Daejeon
fYear
2008
fDate
18-21 May 2008
Firstpage
3534
Lastpage
3537
Abstract
In this paper, we propose a clipping engine (CE) in 3D graphics. A conventional CE shows lower performance as clipping-ratio increases, because the process time of a clipped triangle is much longer than that of a non-clipped triangle. We focus on conserving performance, while clipping-ratio changes. Proposed architecture separates datapath into clip datapath and perspective division & viewport mapping (PDVM) datapath, which makes it possible for CE to handle two triangles at a time. Its performance gain is up to four times of clipping-ratio. It is implemented with 79 k logic gates and 3 kB SRAM in 0.18 um CMOS technology.
Keywords
CMOS integrated circuits; SRAM chips; limiters; logic gates; 3D graphics clipping; CMOS technology; SRAM chips; clip datapath; clipped triangle; clipping-ratio-independent; dual-thread algorithm; logic gates; perspective division; size 0.18 mum; storage capacity 3 Kbit; viewport mapping; CMOS logic circuits; CMOS technology; Computer architecture; Engines; Graphics; Hardware; Logic gates; Performance gain; Pipelines; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4542222
Filename
4542222
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