DocumentCode
1849014
Title
Evaluation of interconnect technologies for power semiconductor devices
Author
Calata, Jesus Noel ; Lu, Guo-Quan ; Luechinger, Christoph
Author_Institution
Dept. of Mater. Sci. & Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
fYear
2002
fDate
2002
Firstpage
1089
Lastpage
1096
Abstract
Electrical interconnection is an important part of device packaging. In packages of power semiconductor devices, wire bonding currently is the predominant interconnect technology; but other technologies such as flip chip, developed for IC chip packaging, and direct solder are being used in newly introduced products. The ever-increasing demand on performance and reliability of power electronics devices and systems has accelerated the research and development for interconnection and packaging. This project was initiated to objectively evaluate different technologies, commercial or developmental, in terms of performance, reliability, fabrication complexity and cost, with high sample-to-sample consistency and statistically significant sample sizes. Three interconnect technologies - wire bond, solder ball, and direct solder - were selected for the initial comparative study. Power devices were attached on direct bond copper (DBC) substrates of identical size, then interconnected by each of the three techniques into testable structures. Thermal cycling is performed under the JEDEC recommended conditions to allow cross-referencing with available data obtained under similar conditions. Monitoring will be done using nondestructive methods such as scanning acoustic microscopy and electrical tests. The procedures for the fabrication and evaluation of the test structures are presented, as are the preliminary experimental results obtained thus far. A description of the cost analysis methodology is also included.
Keywords
flip-chip devices; interconnections; lead bonding; power semiconductor devices; semiconductor device packaging; semiconductor device reliability; soldering; thermal management (packaging); thermal resistance; ultrasonic bonding; cost analysis; direct bond copper substrates; direct solder; fabrication complexity; fabrication cost; failure analysis; flip chip; high sample-to-sample consistency; interconnect technologies; power cycling; power overlay technology; power semiconductor device package; reliability; solder ball; thermal cycling; thermal management; thermal resistance; ultrasonic bonding; wire bond; Acoustic testing; Bonding; Electronics packaging; Fabrication; Integrated circuit packaging; Power semiconductor devices; Power system interconnection; Power system reliability; Semiconductor device packaging; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Thermal and Thermomechanical Phenomena in Electronic Systems, 2002. ITHERM 2002. The Eighth Intersociety Conference on
ISSN
1089-9870
Print_ISBN
0-7803-7152-6
Type
conf
DOI
10.1109/ITHERM.2002.1012579
Filename
1012579
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