Title :
IP delivery for FPGAs using applets and JHDL
Author :
Wirthlin, Michael J. ; McMurtrey, Brian
Author_Institution :
Brigham Young Univ., Provo, UT, USA
Abstract :
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a Web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor.
Keywords :
Java; application specific integrated circuits; circuit CAD; circuit simulation; field programmable gate arrays; industrial property; integrated circuit design; integrated circuit testing; logic CAD; software tools; FPGA IP delivery; FPGA IP evaluation; FPGA circuit design; FPGA circuit test; IP functionality; IP visibility; JHDL design tool; Java applets; Web browser; application-specific circuits; circuit simulation; netlist generation; structural viewing; Circuit simulation; Circuit testing; Field programmable gate arrays; Hardware design languages; Intellectual property; Java; Logic design; Permission; Protection; Web pages;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012584
