Look-up table FPGA synthesis from minimized multi-valued pseudo Kronecker expressions

In this paper we outline a method for Look-up Table-FPGA (LUT-FPGA) synthesis from minimized Multi-Valued Pseudo Kronecker Expressions (MV PSDKROs). By restricting logic minimization to consider only easily mappable expressions, a regular Cellular Architecture (CA) layout without routing overhead is obtained. In this way our method combines logic minimization, mapping and routing. The transformation into the MV domain reduces the area as the number of products in the PSDKRO expression can be further minimized. Deriving the exact minimum MV PSDKRO is known to be hard or even intractable. We address this by applying pruning techniques based on cost estimation and dynamic methods to find suitable variable orderings. Results on a set of MCNC benchmarks show the advantages of the proposed minimization methods