An investigation of self-timed realizations for high-speed digital signal processing

The efficiency of self-timed design styles is evaluated for semi-systolic carry-save architectures. After a classification of the various design options a comparison is carried out for a multiplier considering throughput rate, area consumption and power dissipation. Among the design styles that are investigated in detail is a new pipeline scheme for self-timed circuits. In the sequel it is referred to as four-phase micropipeline with one operation per cycle. It turns out, that the highest throughput rates are obtained for this scheme. For the comparison an optimization procedure has been applied for the choice of the transistor widths in the control logic. The procedure is described briefly. Optimization results for different loads and cycle-times are used to derive rules for the design of micropipelines