DocumentCode :
1849474
Title :
Asynchronous multiple-valued VLSI system based on dual-rail current-mode differential logic
Author :
Hanyu, Takahiro ; Saito, Takahiro ; Kameyama, Michitaka
Author_Institution :
Dept. of Comput. & Math. Scis., Tohoku Univ., Sendai, Japan
fYear :
1998
fDate :
27-29 May 1998
Firstpage :
134
Lastpage :
139
Abstract :
This paper presents a new asynchronous data-transfer in a multi-valued current-mode VLSI circuit based on dual-rail differential logic. In the proposed 2-phase multiple-valued asynchronous communication scheme, R-valued dual-rail complementary signals are used to represent a “data value” while the “spacer” is represented as (0, 0). The sum of R-valued dual-rail complementary values is a constant (R-1) which makes it easy to distinguish a data-arrival state from a data-transition state. This scheme can be extended to any multiple-valued data representation in asynchronous communication. New basic components, a signal-state detector to detect a data-arrival state, and a current-controlled threshold detector to produce dual-rail spacer signals (0,0) are also proposed to realize a compact asynchronous control circuit. It is demonstrated that the overhead for the proposed asynchronous circuit is very small compared with the conventional synchronous multiple-valued current-mode logic approach
Keywords :
CMOS logic circuits; VLSI; asynchronous circuits; current-mode logic; multivalued logic circuits; CMOS; R-valued dual-rail complementary signals; R-valued dual-rail complementary values; asynchronous control circuit; asynchronous data-transfer; asynchronous multiple-valued VLSI system; current-controlled threshold detector; data-arrival state; data-transition state; dual-rail current-mode differential logic; dual-rail spacer signals; multiple-valued data representation; synchronous multiple-valued current-mode logic approach; two-phase multiple-valued asynchronous communication scheme; Logic; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location :
Fukuoka
ISSN :
0195-623X
Print_ISBN :
0-8186-8371-6
Type :
conf
DOI :
10.1109/ISMVL.1998.679323
Filename :
679323
Link To Document :
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