Title :
A generic test and maintenance node for embedded system test
Author :
Lofgren, John D.
Author_Institution :
Martin Marietta Corp., USA
Abstract :
In order to build high performance embedded test systems, a Digital Test and Maintenance ASIC (DTMA) with embedded microprocessor, test bus port, and test network communication ports has been conceived. This DTMA “node” and 2 companion analog data acquisition devices form the basis of a structured, system level design-for-test (DFT) methodology which is applicable to medium or high performance test and maintenance requirements. By offering a robust, minimal-parts-count solution, the methodology also reduces the non-recurring labor costs associated with DFT and the recurring costs of BIT hardware
Keywords :
application specific integrated circuits; automatic test equipment; built-in self test; data acquisition; design for testability; digital integrated circuits; maintenance engineering; peripheral interfaces; production testing; system buses; BIT hardware; Digital Test and Maintenance ASIC; analog data acquisition devices; embedded microprocessor; embedded system test; fault detection; generic test; high performance test; internal bus structure; labor costs; maintenance node; minimal-parts-count solution; recurring costs; system level design-for-test methodology; temperature sensing; test bus port; test network communication ports; Application specific integrated circuits; Communication system control; Control systems; Costs; Design for testability; Embedded system; Hardware; Integrated circuit testing; Production facilities; System testing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528534
