• DocumentCode
    1849632
  • Title

    Wave-parallel computing systems using multiple-valued pseudo-orthogonal sequences

  • Author

    Yuminaka, Yasushi ; Sasaki, Yutaka ; Aoki, Toyohiro ; Higuchi, Tatsuro

  • Author_Institution
    Dept. of Electron. Eng., Gunma Univ.
  • fYear
    1998
  • fDate
    27-29 May 1998
  • Firstpage
    148
  • Lastpage
    153
  • Abstract
    A Wave-Parallel Computing (WPC) technique is proposed to address the interconnection problem in massively interconnected VLSI architectures. The fundamental concept is the multiplexing of several signals onto a single line using orthogonal sequences as information carriers. To reduce MUX/DEMUX circuits, we propose WPC concept which can process multiplexed data directly without decomposition. We investigate the possible implementation of WPC based on the present MOS technology, and propose the multiple valued pseudo-orthogonal m-sequence carrier generation technique. Applications of WPC to neural networks and image processing are discussed, with emphasis on the reduction in the in number of interconnections and on the noise tolerance property
  • Keywords
    CMOS digital integrated circuits; VLSI; binary sequences; image processing equipment; neural chips; MOS technology; MUX/DEMUX circuits; image processing; information carriers; interconnections; massively interconnected VLSI architectures; multiple valued pseudo-orthogonal m-sequence carrier generation technique; multiple-valued pseudo-orthogonal sequences; multiplexed data; neural networks; noise tolerance property; orthogonal sequences; wave-parallel computing systems; Analog computers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
  • Conference_Location
    Fukuoka
  • ISSN
    0195-623X
  • Print_ISBN
    0-8186-8371-6
  • Type

    conf

  • DOI
    10.1109/ISMVL.1998.679327
  • Filename
    679327