RTL C-based methodology for designing and verifying a multi-threaded processor

Author

Séméria, Luc ; Seawright, Andrew ; Mehra, Renu ; Ng, Daniel ; Ekanayake, Arjuna ; Pangrle, Barry

Author_Institution

Synopsys, Inc., Hillsboro, OR, USA

fYear

2002

fDate

2002

Firstpage

123

Lastpage

128

Abstract

A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

Keywords

C language; formal verification; hardware description languages; high level synthesis; logic simulation; multi-threading; parallel processing; C to HDL translation; C-based coding style; RTL C-based methodology; RTL-C to RTL-Verilog equivalence checking; RTL-Verilog verification; gate-level verification; logic design; logic simulation; simultaneous multi-threaded network processor; static scheduling; Application specific integrated circuits; Bridges; Design automation; Design methodology; Design optimization; Hardware design languages; Process design; Processor scheduling; Standards development; Surface-mount technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012606

Filename

1012606