DocumentCode
1849856
Title
HADES-an asynchronous superscalar processor
Author
Elston, C.J. ; Christianson, D.B. ; Findlay, P.A. ; Steven, G.B.
Author_Institution
Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK
fYear
1996
fDate
35123
Firstpage
42644
Lastpage
42649
Abstract
Hades is a generic processor architecture suitable for both single and multiple-instruction-issue asynchronous implementation. This paper discusses Hades, emphasising performance in the presence of instruction sequences exhibiting Read-After-Write (RAW) dependencies. Two schemes are considered. Firstly, a register file optimisation that allows easier read access to data in the case of RAW dependencies. Secondly, an operand forwarding mechanism, Decoupled Operand Forwarding, that forwards data between instructions yet separates forwarding from other pipeline operations. Hardware simulations of Hades indicate that register file optimisation improves performance by 6% and Decoupled Operand Forwarding increases performance by 15%; in combination performance is bettered by 16%. A further result suggests that optimising asynchronous communication in Hades improves performance by 30%
Keywords
asynchronous circuits; microprocessor chips; parallel architectures; pipeline processing; HADES; asynchronous superscalar processor; decoupled operand forwarding; generic processor architecture; instruction sequences; multiple-instruction-issue asynchronous implementation; operand forwarding mechanism; pipeline operations; read-after-write dependencies; register file optimisation;
fLanguage
English
Publisher
iet
Conference_Titel
Design and Test of Asynchronous Systems, IEE Colloquium on
Conference_Location
London
Type
conf
DOI
10.1049/ic:19960255
Filename
543169
Link To Document