Layout-aware synthesis of arithmetic circuits

We propose a new module generation/synthesis algorithm for arithmetic circuits utilizing carry-save-adder (CSA) modules, which not only optimizes the circuit timing but also generates a much more regular interconnect topology of the final circuits. Specifically, we propose a two-step algorithm. In Phase 1 (CSA module generation), we propose an optimal-timing CSA module generation algorithm for an arithmetic expression under a general CSA timing model. In Phase 2 (Bit-level interconnect refinements), we optimally refine the interconnects between the CSA modules while retaining the global CSA-tree structure produced by Phase 1. It is shown that the timing of the circuits produced by our approach is equal or close to that obtained in most test-cases (even without including the interconnect delay), and at the same time, the interconnects in the layout are significantly shorter and more regular.