DocumentCode
1850250
Title
Effective diagnostics through interval unloads in a BIST environment
Author
Wohl, Peter ; Waicukauski, John A. ; Patel, Sanjay ; Maston, Greg
Author_Institution
Synopsys Inc., Williston, VT, USA
fYear
2002
fDate
2002
Firstpage
249
Lastpage
254
Abstract
Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test interface language (STIL). The implementation of the proposed method is presented and analyzed.
Keywords
built-in self test; fault diagnosis; logic simulation; BIST environment; effective diagnostics; fault diagnosis resolution; gate-level faults; inherent fault diagnostic challenges; interval unloads; interval-based scan-unload method; logic built-in self test; standard test-interface language; test cost reduction; test quality; tester fail-data collection; Automatic testing; Built-in self-test; Circuit testing; Failure analysis; Hardware; Logic testing; Manufacturing; Permission; Phase shifters; Phased arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012630
Filename
1012630
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