Title :
Transformation based communication and clock domain refinement for system design
Author :
Sander, Ingo ; Jantsch, Axel
Author_Institution :
R. Inst. of Technol., Stockholm, Sweden
Abstract :
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system model into an implementation model. The methodology defines two classes of design transformations: (1) semantic-preserving transformations and (2) design decisions. In particular we present and illustrate communication and clock domain refinement by way of a digital equalizer system.
Keywords :
circuit CAD; clocks; equalisers; formal verification; integrated circuit design; system-on-chip; ForSyDe methodology; SoC; clock domain refinement; design transformations; digital equalizer system; formal system model; formal transformation methods; implementation model; semantic-preserving transformations; system level design; transformation based communication; Clocks; Computational modeling; Design automation; Design engineering; Design methodology; Equalizers; Hardware; Integrated circuit modeling; Permission; System-on-a-chip;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012636
