Low-swing clock domino logic incorporating dual supply and dual threshold voltages

High-speed domino logic is now prevailing in the performance critical block of chips. A Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost transition speed in the proposed circuitry, a well-established dual threshold voltage technique is exploited. A dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in the clock tree and logic gates effectively. A Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that the dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.