Title :
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
Author :
Karnik, Tanay ; Ye, Yibin ; Tschanz, James ; Wei, Liqiong ; Burns, Steven ; Govindarajulu, Venkatesh ; De, Vivek ; Borkar, Shekhar
Author_Institution :
Circuit Res., Intel Labs., Hillsboro, OR, USA
Abstract :
We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5× larger computation runtime than iSTATS due to its iterative nature
Keywords :
circuit optimisation; integrated circuit design; iterative methods; logic CAD; microprocessor chips; Lagrangian relaxation based tool; VLSI; computation runtime; design automation solutions; design migration; device sizing; heuristic iterative optimization flow; high performance microprocessors; iSTATS; iterative nature; simultaneous dual-Vt allocation; total power optimization; CMOS logic circuits; Delay; Design automation; Design optimization; Energy consumption; Iterative algorithms; Lagrangian functions; Microprocessors; Permission; Threshold voltage;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012674
