Title :
Analysis of power consumption on switch fabrics in network routers
Author :
Ye, T.T. ; Benini, Luca ; De Micheli, Giovanni
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.
Keywords :
integrated circuit interconnections; integrated circuit modelling; low-power electronics; multistage interconnection networks; switching networks; system-on-chip; telecommunication network routing; Banyan network; architectural exploration; bit-level accuracy; dynamic power consumption; ingress/egress ports; interconnect wire length estimation; interconnect wire power consumption; interconnect wires; internal buffers; low power high performance network router designs; modeling methodologies; network on chip; network routers; node switches; power consumption; simulation platform; switch fabric architectures; switch fabrics; system on chip; traffic throughput; Analytical models; Energy consumption; Fabrics; Integrated circuit interconnections; Intelligent networks; Packet switching; Switches; Switching circuits; Telecommunication traffic; Traffic control;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012681
