Design of a concurrent dual-band receiver front-end in 0.18 μm CMOS for WLANs IEEE 802.11a/b/g applications

Author

Jou, Christina F. ; Cheng, Kuo-Hua ; Lien, Wei-Cheng ; Wu, Chun Hsien ; Yen, Chin Hsien

Author_Institution

Inst. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

A fully monolithic dual-band concurrent receiver chip for IEEE 802.11a, 802.11b and 802.11g applications is presented in a 0.18-μm CMOS 1P6M technology. A low IF architecture was chosen in order to achieve a low-cost and low-power solution with a high level of integration compared to direct conversion architecture. This mixer can operate as a sub-harmonic mixer and even as a traditional Gilbert mixer if LO ports connecting to each other to find two RF inputs and two LO inputs. For a 1.8 V power supply, the overall power consumptions are 84.3 mW, with 3.5 dB and 6.3 dB overall receive-chain noise figure for 2.45 GHz and 5.25 GHz, respectively.

Keywords

CMOS integrated circuits; MMIC mixers; UHF integrated circuits; UHF mixers; integrated circuit design; low-power electronics; power consumption; radio receivers; wireless LAN; 0.18 micron; 1.8 V; 2.45 GHz; 3.5 dB; 5.25 GHz; 6.3 dB; 84.3 mW; CMOS technology; Gilbert mixer; IEEE 802.11a applications; IEEE 802.11b applications; IEEE 802.11g applications; integrated circuit design; low IF architecture; low power electronics; monolithic dual band concurrent receiver chip; power consumption; subharmonic mixer; Bandwidth; CMOS technology; Dual band; Filters; Frequency synthesizers; OFDM; Radio frequency; Spread spectrum communication; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353926

Filename

1353926