High-level synthesis of multiple-precision circuits independent of data-objects length

Author

Molina, M.C. ; Mendías, J.M. ; Hermida, R.

Author_Institution

Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain

fYear

2002

fDate

2002

Firstpage

612

Lastpage

615

Abstract

This paper presents an heuristic method to perform the high-level synthesis of multiple-precision specifications. The scheduling is based on the balance of the number of bits calculated per cycle, and the allocation on the bit-level reuse of the hardware resources. The implementations obtained are multiple-precision datapaths independent of the number and widths of the specification operations. As a result impressive area savings are achieved in comparison with conventional algorithms implementations.

Keywords

high level synthesis; processor scheduling; resource allocation; signal processing; DSP applications; allocation; area savings; data-object length independence; hardware resources bit-level reuse; heuristic method; high-level synthesis; multiple-precision circuits; multiple-precision datapaths; multiple-precision specifications; scheduling; Algorithm design and analysis; Circuits; Design optimization; Digital signal processing; Hardware; High level synthesis; Permission; Processor scheduling; Resource management; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012698

Filename

1012698