DocumentCode
1852070
Title
Test generation for (sequential) multi-valued logic networks based on genetic algorithm
Author
Keim, Martin ; Drechsler, Nicole ; Drechsler, Rolf ; Becker, Bernd
Author_Institution
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear
1998
fDate
27-29 May 1998
Firstpage
215
Lastpage
220
Abstract
In this paper we present a test pattern generation tool for combinational Multi-Valued Logic Networks (MVLN) and Sequential Multi-Valued Logic Networks (SMVLN). The test pattern generator is based on a Genetic Algorithm. The tool can generator test patterns with respect to the stuck-at-fault model and skew fault model for SMVLNs with up to some thousand gates. A large set of experimental results is given to demonstrate the efficiency of the approach
Keywords
genetic algorithms; logic testing; multivalued logic circuits; MVLN; SMVLN; multi-valued logic networks; skew fault model; stuck-at-fault model; test pattern generation; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Genetic algorithms; Logic testing; Multivalued logic; Sequential analysis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location
Fukuoka
ISSN
0195-623X
Print_ISBN
0-8186-8371-6
Type
conf
DOI
10.1109/ISMVL.1998.679435
Filename
679435
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