DocumentCode :
185212
Title :
Hardware event handling in the hardware real-time operating systems
Author :
Moisuc, Elena-Eugenia Ciobanu ; Larionescu, Alexandru-Bogdan ; Ungurean, Ioan
Author_Institution :
Fac. of Electr. Eng. & Comput. Sci, Stefan cel Mare Univ. of Suceava, Suceava, Romania
fYear :
2014
fDate :
17-19 Oct. 2014
Firstpage :
54
Lastpage :
58
Abstract :
An important issue related to Real-Time Operating Systems is the handling of interrupts, timers, mutexes, watchdog timers, synchronization and communication directives as unitary events. In order to obtain a predictable response time for the different types of events that occur simultaneously, it is necessary to have a prioritization mechanism for them. Therefore, this paper proposes a hardware mechanism for handling the events enumerated above, in order to improve the software solution, which is not efficient because it generates delays. The method is implemented in n-tasks Multi Pipeline Register Architecture, that is a microcontroller architecture with Real-Time Operating Systems capabilities implemented in hardware, which allows switching time between tasks of one processor cycle and a response time to events of up to 1.5 processor cycles.
Keywords :
microcontrollers; operating systems (computers); pipeline processing; real-time systems; hardware event handling; hardware real-time operating system; microcontroller architecture; n-tasks multipipeline register architecture; prioritization mechanism; Computer architecture; Context; Hardware; Operating systems; Pipelines; Real-time systems; Registers; embedded systems; event handling; hardware scheduler; pipeline register; real-time operating systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, Control and Computing (ICSTCC), 2014 18th International Conference
Conference_Location :
Sinaia
Type :
conf
DOI :
10.1109/ICSTCC.2014.6982390
Filename :
6982390
Link To Document :
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