DocumentCode :
1852191
Title :
Multiple-valued logic minimization using universal literals and cost tables
Author :
Fraser, Blair ; Dueck, Gerhard W.
Author_Institution :
Dept. of Math., Comput. & Inf. Syst., St. Francis Xavier Univ., Antigonish, NS, Canada
fYear :
1998
fDate :
27-29 May 1998
Firstpage :
239
Lastpage :
244
Abstract :
We propose a minimization algorithm that combines cost tables and simulated annealing. Unlike other minimization procedures that use cost tables, our method does not rely on the enumeration of all minterms, it works directly with the expression (a sum of product terms). We tested our method with a cost table obtained from current mode CMOS. The algorithm can be readily adapted to any other technology by simply replacing the cost table. The technology dependency is limited to the cost table. Results from our implementation are very encouraging
Keywords :
minimisation of switching nets; multivalued logic; cost table; current mode CMOS; minimization; minimization algorithm; multiple-valued logic minimization; simulated annealing; universal literals; CMOS logic circuits; CMOS technology; Computational modeling; Cost function; Councils; Information systems; Logic circuits; Mathematics; Minimization methods; Simulated annealing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location :
Fukuoka
ISSN :
0195-623X
Print_ISBN :
0-8186-8371-6
Type :
conf
DOI :
10.1109/ISMVL.1998.679449
Filename :
679449
Link To Document :
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