DocumentCode
1852695
Title
Look-up tables (LUTs) for multiple-valued, combinational logic
Author
Sheikholeslami, Ali ; Yoshimura, Ryuji ; Gulak, P. Glenn
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
1998
fDate
27-29 May 1998
Firstpage
264
Lastpage
269
Abstract
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiple-valued LUT can be implemented using both current-mode and voltage-mode techniques, reducing the transistor count to half compared to that of a binary implementation. Two main applications for multiple-valued LUTs are multiple-valued FPGAs and intelligent memories. An FPGA uses a LUT as a generic logic block to provide programmability. In an intelligent memory, a multiple-valued LUT is added in the Y-decoder section to facilitate simple mathematical operations on the stored digits. An FFT operation is used as an example in this paper to illustrate how a multiple-valued LUT can be beneficial
Keywords
combinational circuits; field programmable gate arrays; multivalued logic; table lookup; FPGAs; Look-Up Tables; combinational logic; intelligent memories; multiple-valued LUT; multiple-valued logic; CMOS logic circuits; Councils; Information systems; Joining processes; Logic functions; MOSFETs; Silicon; Table lookup; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location
Fukuoka
ISSN
0195-623X
Print_ISBN
0-8186-8371-6
Type
conf
DOI
10.1109/ISMVL.1998.679468
Filename
679468
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