Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. Since, multiple-valued pass-transistor network is realized by multiple-valued threshold-literal and pass-switch functions, it can be designed compactly by using floating-gate MOS transistors. As an example of typical logic-in memory VLSI systems, a fully parallel magnitude comparator is also presented. The performance of the proposed multiple-valued logic-in-memory VLSI is about 26 times higher than that of the corresponding implementation based on a binary content-addressable memory under a 0.8 μm flash EEPROM technology. Moreover, its effective chip area and power dissipation are reduced to about 42 and 20 percents, respectively, in comparison with those of binary implementation