Title :
A subtraction-based adder amplifier for 10b 50 MS/s low-power pipelined-ADC´s
Author :
Kim, Gil Su ; Ki, Hoon Jae ; Kim, Soo Won ; Yoo, Jae Tack
Author_Institution :
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
Abstract :
We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC´s which are employed for high-speed signal processing, i.e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50 MS/s pipelined analog-to-digital converter.
Keywords :
adders; amplifiers; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; low-power electronics; pipeline processing; high speed ADC; high speed signal processing; image processing; integrated circuit design; low power pipelined ADC; pipelined analog-digital converter; subtraction based adder amplifier; Adders; Circuits; Delay; Energy consumption; Impedance; Linearity; Mirrors; Operational amplifiers; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
DOI :
10.1109/MWSCAS.2004.1353995
