Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter

Author

Lee, Tsung-Sum ; Luo, Li-Dyi ; Lin, Chin-Sheng

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

A CMOS 8-bit, 33.3 MS/s flash ADC with ±1.5 V power supply is developed through the use of a CMOS low-power high-speed fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than ±0.3 LSB. Signal-to-(noise and distortion) ratio is 46.2 dB at a sampling rate of 33.3 MS/s and input frequency of 4 MHz. The power dissipation is 106 mW at 33.3 MS/s with ±1.5 V power supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); high-speed integrated circuits; integrated circuit design; integrated circuit noise; low-power electronics; 1.5 V; 106 mW; 4 MHz; CMOS ADC; differential comparator; differential nonlinearity error; digital circuit noise; fully differential flash analog-digital converter; high speed comparator; integrated circuit design; low power electronics; low voltage ADC; power dissipation; signal-distortion ratio; signal-noise ratio; Analog-digital conversion; CMOS technology; Circuits; Decoding; Distortion; Inverters; Power supplies; Sampling methods; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354001

Filename

1354001