Temperature aware SoC design for reduced leakage power and enhanced reliability

Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the chips but also increases leakage-power dissipation and reduces interconnect lifetime. Furthermore, the floorplan of a System-on-a-Chip (SoC) has a significant impact on the temperature profile and leakage power, requiring early analysis of the SoC temperature profiles. We will talk about a system level leakage estimation methodology that considers the floorplan of the SoC and also the positive feedback relation between temperature and leakage power. We also talk about a system-level Leakage-Aware Floorplanner (LEAF) that optimizes floorplans for temperature-aware leakage power along with the traditional metric of area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage-aware floorplanning. Temperature also has a serious effect on the Mean Time to Failure (MTF) of interconnects because of electromigration. To address this issue, we have developed a Temperature Aware Global Router (TAGORE) that reduces the probability of chip failure due to interconnect failures. TAGORE achieves a reduction in the probability of failure by routing more wires in the colder regions of the chip and fewer wires in the hotter regions of the chip. We observed that TAGORE reduced the number of wires in the hottest region of a chip by up to 19.95% and by an average of 12.29%. This resulted in a decrease in the failure rate by up to 292 failures per million hours of operation. This approach to reliability improvement does not require any addition of redundant wires or vias. We also have an analytical examination of the reduction in the probability of interconnect failure and the failure rate due to temperature aware global routing.