An area-efficient design for Programmable memory Built-In Self-Test

As the progress of deep submicron technology, embedded memory grows greatly in the System-on-Chip design. An efficient test method with relatively low cost is required for mass production process. Programmable Built-in Self-Test (P-MBIST) solution provides a certain degree of flexibility with reasonable hardware cost, based on the customized controller/processor. In this work, we propose a hardware sharing architecture for P-MBIST design. Through sharing the common address generator and controller, the area overhead of P-MBIST circuit can be significantly reduced. Higher testing speed can be achieved by inserting two pipeline stages. Finally, the proposed P-MBIST circuit can be automatically generated from the user-defined configuration file.