A highly efficient digital down converter in wide band digital radar receiver

An improved design method for digital down converter (DDC) is proposed here to satisfy the increased requirements for miniaturization and low power consumption of signal processor in digital wide band radar receiver. Using the sampling technique that the sampling frequency equals to four times the intermediate frequency (IF) of echo signals, combining with the tap coefficient characteristics of half band finite impulse response (FIR) filter, a specific hardware structure is generated after detailed theoretical derivation. With this structure, the signal processing complexity and resource utilization are both reduced significantly, especially the multiplier blocks. Finally, compared with conventional design method, the design results based on FPGA show that the logical resources are saved by 83.65% and the power consumption is reduced by 110 mW, indicating the validity and good engineering applicability of this method.