DocumentCode
1853163
Title
A scalable and accurate rectilinear Steiner minimal tree algorithm
Author
Wong, Yiu-Chung ; Chu, Chris
Author_Institution
Rio Design Autom., Santa Clara, CA
fYear
2008
fDate
23-25 April 2008
Firstpage
29
Lastpage
34
Abstract
FLUTE is a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm particularly suitable for VLSI applications. It is optimal for nets up to degree 9 and is still very accurate for nets up to degree 30. However, for higher degree nets, the original FLUTE algorithm is not effective. In this paper, we present an improvement of FLUTE which is more effective in handling nets with degree tens or more. The main idea is to partition a net according to a spanning tree into small subnets that can be handled effectively by the original FLUTE algorithm. Several novel techniques are proposed to partition a net into small subnets and to merge the Steiner trees for the subnets together. Some improvements of the original FLUTE algorithm, and a scheme to allow users to control the tradeoff between accuracy and runtime are also presented. We show experimentally that the resulting algorithm FLUTE-3.0 achieves a much better accuracy-runtime tradeoff than the original FLUTE algorithm for degree 30 or more. It produces better quality of result than the well-known near-optimal BUS algorithm in a runtime shorter than the highly scalable BGA algorithm. FLUTE-3.0 is also highly scalable. It can route a 3-million-pin net in about 25 minutes.
Keywords
VLSI; integrated circuit design; integrated circuit modelling; logic partitioning; merging; trees (mathematics); FLUTE algorithm; VLSI applications; VLSI design; aggressive-merge algorithm; net partitioning; quality tradeoff; rectilinear Steiner minimal tree algorithm; runtime control; tree-based net breaking technique; Algorithm design and analysis; Design automation; Iterative algorithms; Joining processes; Partitioning algorithms; Runtime; Steiner trees; Table lookup; Tree graphs; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-1616-5
Electronic_ISBN
978-1-4244-1617-2
Type
conf
DOI
10.1109/VDAT.2008.4542405
Filename
4542405
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