Energy exploration and reduction of SDRAM memory systems

In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use. We build an in-house energy simulator for SDRAM main memory systems based on cycle-accurate energy measurement and state-machine-based characterizations which independently characterize dynamic and static energy. We explore energy behavior of the memory systems by changing design parameters such as processor clock, memory clock and cache configuration. Finally we propose new energy reduction techniques for the address bus and practical mode control schemes for the SDRAM devices. We save 10.8 mJ and 12 mJ, 40.2% and 14.5% of the total energy, for 24 M instructions of an MP3 decoder and a JPEG compressor, using a typical 32-bit, 64 MB SDRAM memory system.