Ultra-low leakage MTCMOS circuits with regular-Vt long channel stacked footers for deep sub-100 nm technologies

This paper demonstrates that regular-V_t long channel stacked and optimally tapered headers/footers can be used for ultra-low leakage circuits at Iow-VddS with dramatic leakage reduction over earlier schemes. Our proposed schemes take advantage of the fact that the leakage saving of two stacked OFF devices as compared to a single OFF device increase rapidly when the sub-threshold slope reduces (improves).