Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Author

Huang, Xuejue ; Restle, Phillip ; Bucelot, Thomas ; Cao, Yu ; King, Tsu-Jae

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2002

fDate

2002

Firstpage

19

Lastpage

22

Abstract

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

Keywords

circuit optimisation; digital integrated circuits; equivalent circuits; high-speed integrated circuits; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; synchronisation; timing circuits; HF effects; Power4 chip; RLC modeling approach; electromagnetic simulations; high frequency effects; inductance effects; loop-based interconnect modeling methodology; multi-GHz clock network design; optimization approach; proximity effects; Analytical models; Circuit simulation; Clocks; Delay; Design optimization; Frequency locked loops; Inductance; Integrated circuit interconnections; Proximity effect; Solid modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012758

Filename

1012758