Title :
Testing the hold time fault for large industrial design
Author :
Tsai, Kun-Han ; Rajski, Janusz
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
Abstract :
A new fault model and ATPG algorithm are proposed to target the hold time fault, which is guided by the timing information (e.g. from SDFfile) to detect the fault through the shortest path to maximize the probability of detecting the hold time fault due to small delay defects or process variations. The fault population is linear to the number of the state elements in the design and the fault list is automatically derived by the algorithm, which makes the solution robust and practical on large design over 10M gates.
Keywords :
automatic test pattern generation; fault diagnosis; timing; ATPG algorithm; fault model; fault population; hold time fault; large industrial design; process variations; small delay defects; testing; timing information; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Costs; Delay effects; Fault detection; Fault location; Timing;
Conference_Titel :
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1616-5
Electronic_ISBN :
978-1-4244-1617-2
DOI :
10.1109/VDAT.2008.4542421
