DocumentCode
1853521
Title
A genetic algorithm for the rectilinear Steiner tree in 3-D VLSI layout design
Author
Kanemoto, Yukio ; Sugawara, Ryuta ; Ohmura, Michiroh
Author_Institution
Hiroshima Inst. of Technol., Japan
Volume
1
fYear
2004
fDate
25-28 July 2004
Abstract
As manufacturing technology has advanced in recent years, 3-D ICs in which circuits are piled on top of each other have been the focus of attention. A rectilinear Steiner minimum tree is one of the most important problems in the layout design of VLSI. This paper proposes a genetic algorithm for the rectilinear Steiner minimum tree with consideration of the diameter in 3-D VLSI layout design. The experimental results are also shown.
Keywords
VLSI; genetic algorithms; integrated circuit layout; trees (mathematics); 3D IC; 3D VLSI layout design; genetic algorithm; manufacturing technology; rectilinear Steiner minimum tree; Algorithm design and analysis; Circuits; Genetic algorithms; Manufacturing; Propagation delay; Space technology; Steiner trees; Tree graphs; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN
0-7803-8346-X
Type
conf
DOI
10.1109/MWSCAS.2004.1354028
Filename
1354028
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