Instruction decode mechanism for embedded real-time Java processor JPOR-32

In this paper, taking JPOR-32 as an example, the mechanism of instruction decode (ID) for embedded real-time Java processor is presented. In light of the complex format of Java bytecodes instructions and the predictable requirement, a two-stage ID mechanism which provides effective support for predictability and efficiency of the processor is adopted. In ID stage one, complex instructions are converted to microinstructions through the mechanism of microprogram address mapping, and the reorganization of bytecodes instructions is performed with buffer. ID stage two provides architectural support for operands revision for predictable WCET, assists stage one in instruction recognition and conversion, and generates control signals for the following execution and memory access stage.