The embedded SCR NMOS and low capacitance ESD protection device

Author

Lee, Jian-Hsing ; Wu, YH ; Peng, KR ; Chang, RY ; Yu, TL ; Ong, TC

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2002

fDate

2002

Firstpage

93

Lastpage

96

Abstract

Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, and a very low capacitance (∼50 fF) ESD protection (LCESD) device are developed successfully for output pad and input pad, respectively. In addition, a protection scheme, combining the power protection device and a n+ guard-ring, is proposed and proven to be capable of protecting four directions ESD zapping and without increasing the LCESD device capacitance.

Keywords

CMOS integrated circuits; MOSFET; capacitance; electrostatic discharge; thyristors; 50 fF; DC I-V characteristics; ESCR; LCESD device capacitance; NMOS transistor; drain region; embedded SCR NMOS; low capacitance ESD protection device; n+ guard-ring; n-well; p+ diffusion; power protection device; Capacitance; Electrostatic discharge; Equivalent circuits; MOS devices; Protection; Radio frequency; Semiconductor device manufacture; Stress; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012774

Filename

1012774