Title :
Post routing performance optimization via tapered link insertion and wiresizing
Author :
Xue, Tianxiong ; Kuh, Ernest S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can reduce both maximum delay and skew of an existing routing topology by tapered little insertion and non-uniform wiresizing. It uses the Sequential Quadratic Programming method for constrained optimization. Experimental results show that our approach can improve performance significantly and consume less area than uniform wiresizing
Keywords :
circuit layout; circuit layout CAD; circuit optimisation; electronic engineering computing; minimisation of switching nets; network routing; quadratic programming; Sequential Quadratic Programming method; clock routing algorithms; post routing performance optimization; routing topology; tapered link insertion; wiresizing; Circuit topology; Clocks; Constraint optimization; Delay estimation; Integrated circuit interconnections; Network topology; Quadratic programming; Routing; Tree graphs; Upper bound;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.528550