DocumentCode
1853893
Title
A 16 kb 1T1C FeRAM test chip using current-based reference scheme
Author
Siu, Joseph Wai Kit ; Eslami, Yadollah ; Sheikholeslami, Ali ; Gulak, P. Glenn ; Endo, Toru ; Kawashima, Shoichiro
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
2002
fDate
2002
Firstpage
107
Lastpage
110
Abstract
A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 μm FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.
Keywords
cellular arrays; ferroelectric storage; random-access storage; reference circuits; 0.35 micron; 16 kbit; 1T1C FeRAM test chip; 3 V; 62 ns; access time; current-based reference scheme; memory cells; reference cells; reference generation scheme; Degradation; Fatigue; Ferroelectric films; Ferroelectric materials; Laboratories; Nonvolatile memory; Random access memory; Robustness; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Print_ISBN
0-7803-7250-6
Type
conf
DOI
10.1109/CICC.2002.1012777
Filename
1012777
Link To Document