Low-power sequential access memory design

Author

Moon, Joong-Seok ; Athas, William C. ; Beerel, Peter A. ; Draper, Jeffrey T.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2002

fDate

2002

Firstpage

111

Lastpage

114

Abstract

This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16×16-b SAM and one 64×16-b SAM (consisting of four 16×16-b banks) has been designed, fabricated, and evaluated using a 0.25-μm CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16×16-b SAM and the 64×16-b SAM are 344 μW and 358 μW respectively, demonstrating power dissipation that is largely independent of SAM size

Keywords

CMOS memory circuits; VLSI; integrated circuit design; low-power electronics; memory architecture; 0.25 micron; 1.2 V; 344 muW; 358 muW; 40 MHz; CMOS process; high performance; locally-communicating sequencers; low-power memory design; sequential access memory; Clocks; Decoding; Frequency measurement; Power dissipation; Power measurement; Random access memory; Semiconductor device measurement; Size measurement; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Conference_Location

Orlando, FL

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012778

Filename

1012778