DocumentCode
1854014
Title
Design of an OFDMA baseband receiver for 3GPP long-term evolution
Author
Chu, ChinWei ; Lee, ChiaChing ; Huang, YuanHao
Author_Institution
Inst. of Commun. Eng. & Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu
fYear
2008
fDate
23-25 April 2008
Firstpage
196
Lastpage
199
Abstract
In this paper, we propose a downlink OFDMA processor based on the 3GPP LTE. This processor supports scalable bandwidth for different OFDMA modes. A low-cost sampling rate conversion is employed to obtain different sampling rates for different bandwidths. Timing and frequency synchronization are then designed to recover the time and frequency mismatch between the transmitter and receiver. Afterward, sampling clock offset is tracked and compensated in the frequency domain. Finally, reconfigurable channel estimation and equalization are designed for optimal performance. The circuit architecture is designed and simulated to show that its performance meets the system requirement.
Keywords
3G mobile communication; OFDM modulation; channel estimation; equalisers; microprocessor chips; receivers; synchronisation; 3GPP long-term evolution; baseband receiver; downlink OFDMA processor; frequency domain; frequency synchronization; low-cost sampling rate conversion; reconfigurable channel equalization; reconfigurable channel estimation; sampling clock offset; scalable bandwidth; timing synchronization; Bandwidth; Baseband; Channel estimation; Clocks; Downlink; Frequency domain analysis; Frequency synchronization; Sampling methods; Timing; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-1616-5
Electronic_ISBN
978-1-4244-1617-2
Type
conf
DOI
10.1109/VDAT.2008.4542446
Filename
4542446
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