Burst mode: a new acceleration mode for 128-bit block ciphers

Author

Mitsuyama, Yukio ; Andales, Zaldy ; Onoye, Takao ; Shirakawa, Isao

Author_Institution

Dept. Inf. Syst. Eng, Osaka Univ., Japan

fYear

2002

fDate

2002

Firstpage

151

Lastpage

154

Abstract

"Burst mode" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit CAD; coprocessors; cryptography; digital signal processing chips; hardware-software codesign; 1.3 Gbit/s; 128 bit; AES; Advanced Encryption Standard; acceleration mode; accelerator core; application specific signal processor; burst mode; cipher mode; encryption operation; hardware/software codesign; high performance implementation; next generation block cipher algorithms; plaintext blocks; software-based block cipher; stream cipher mechanism; throughput improvement; Acceleration; Costs; Cryptography; Hardware; High performance computing; Informatics; Information systems; Internet; Mobile communication; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012786

Filename

1012786