Bottleneck removal algorithm for dynamic compaction and test cycles reduction

We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinational and sequential circuits. Several dynamic algorithms for compaction in combinational circuits have been proposed but, to the best of our knowledge, no dynamic method has been reported in the literature for compaction in non scan sequential circuits. Our algorithm is based on two key ideas: (1) we first identify bottlenecks that prevent vector compaction and test cycle reduction for test sequences generated thus far, and (2) future test sequences are generated with an attempt to eliminate bottlenecks of earlier generated test sequences. If all bottlenecks of a sequence are eliminated, then the sequence is dropped from the test set. The final test set generated by our algorithm is minimal in the following sense. Static vector compaction or test cycle reduction using set-covering or extended set-covering approaches (for example, reverse or any other order of fault simulation, with any specification of unspecified inputs in test sequences) cannot further reduce the number of vectors. Experimental results on scan and non scan sequential circuits are reported to demonstrate the effectiveness of our algorithm