The design of CMOS cellular neural network (CNN) using the neuron-bipolar junction transistor (νBJT)

Author

Yeh, Chiou-Ling ; Wu, Chug-Yu

Volume

4

fYear

1999

fDate

1999

Firstpage

2337

Abstract

In this paper, two CMOS implementations of the cellular neural network (CNN) are presented based on the neuron-bipolar junction transistor (νBJT) which consists of the parasitic PNP bipolar junction transistor and the spreading base resistor array in the CMOS process. In the first design, the νBJT is used to implement the neuron and weights of the cell. In the second design, it is used to implement the current summation and weights of the cell, and a diode structure is proposed to realize the neuron. For programmable capability the resistor in the νBJT can be replaced by a tunable MOS resistor. The two kinds of circuits have been designed and fabricated in 0.6 μm single-poly-triple-metal n-well CMOS process

Keywords

CMOS integrated circuits; SPICE; bipolar transistor circuits; cellular neural nets; circuit simulation; integrated circuit design; neural chips; νBJT; 0.6 mum; CMOS cellular neural network design; CNN; HSPICE simulation; cell summation; cell weights; diode structure; neuron-bipolar junction transistor; parasitic PNP bipolar junction transistor; programmable capability; single-poly-triple-metal n-well CMOS process; spreading base resistor array; tunable MOS resistor; CMOS process; Cellular neural networks; Current limiters; Diodes; Neural network hardware; Neurons; Operational amplifiers; Resistors; Tunable circuits and devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1999. IJCNN '99. International Joint Conference on

Conference_Location

Washington, DC

ISSN

1098-7576

Print_ISBN

0-7803-5529-6

Type

conf

DOI

10.1109/IJCNN.1999.833430

Filename

833430